VHDL CODE ( NOT INVOLVE SORTING BUT GIVES SAME RESULT )

WE HAVE DONE DATA FLOW MODELLING FOR ONE BLOCK AND STRUCTURAL FOR OTHER SIMILAR BLOCKS
DATA FLOW OF ONE FULL ADDER MODULE IS :
----------------------------------------------------------------------------------
-- Company: ait minor project under c..s. vinitha
-- Engineer: sahil,chandan,suhaib
--
-- Create Date:    20:35:11 10/14/2013
-- Design Name:
-- Module Name:    singleFA - data flow
-- Project Name: media filter using full addder
-- Target Devices: mobile phones
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity singleFA is
    Port ( x1 : in  STD_LOGIC;
           x2 : in  STD_LOGIC;
           x3 : in  STD_LOGIC;
           s : out  STD_LOGIC;
           v : out  STD_LOGIC);
end singleFA;

architecture Behavioral of singleFA is

begin

s<=(x1 and x2) or (x2 and x3) or (x3 and x1);
v<=x1 xor x2 xor x3;

end Behavioral;


end Behavioral;

CODE FOR COMPLETE SEVEN FULL ADDER MAKING COMPLETE FILTER :

----------------------------------------------------------------------------------
-- Company: ait minor project under c.s. vinitha
-- Engineer: sahil,chandan,suhaib
--
-- Create Date:    20:46:41 10/14/2013
-- Design Name:
-- Module Name:    filter - Behavioral
-- Project Name: median filter using full adder
-- Target Devices: mobile phones
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity filter is
    Port ( x1 : in  STD_LOGIC;
           x2 : in  STD_LOGIC;
           x3 : in  STD_LOGIC;
           x4 : in  STD_LOGIC;
           x5 : in  STD_LOGIC;
           x6 : in  STD_LOGIC;
           x7 : in  STD_LOGIC;
           x8 : in  STD_LOGIC;
           x9 : in  STD_LOGIC;
           MED : out  STD_LOGIC;
           VALUE : out  STD_LOGIC);
end filter;

architecture Structural of filter is

component singleFA
port(x1,x2,x3:in  STD_LOGIC;s,v: out  STD_LOGIC);
end component;

signal s1,s2,s3,s4,s5,s6,v1,v2,v3,v4,v5,v6:STD_LOGIC;

begin

f1:singleFA port map(x1,x2,x3,s1,v1);
f2:singleFA port map(x4,x5,x6,s2,v2);
f3:singleFA port map(x7,x8,x9,s3,v3);
f4:singleFA port map(s1,s2,s3,s4,v4);
f5:singleFA port map(v1,v2,v3,s5,v5);
f6:singleFA port map(v4,s5,v5,s6,v6);
f7:singleFA port map(s4,s6,v6,MED,VALUE);


end Structural;